Intelligent Hearing Systems Corp. (IHS), plans to develop an open architecture hardware and software system that will allow researchers to conduct a wide range of studies involving multi-channel acoustic input and output for psychophysical research. The proposed architecture will capitalize on 30 years of digital signal processor (DSP) based hardware and software development experience at IHS used for highly precise synchronized acoustical stimulus generation and data acquisition. The system will include a Universal Serial Bus (USB) controller to direct data, DSP code and control instructions to and from a control computer and memory shared with the DSP. This architecture provides a wide range of flexibility by allowing various applications and processing strategies to be uploaded at any time. Multiple levels of user programmability will be provided in order to suit the needs of researchers of various technical capabilities including: 1) Signals generation and acquisition using programs such as MatLab or integrated advanced speech processing TF32 software developed at the University of Wisconsin - Madison. 2) User developed application in various programming languages using provided Dynamically Linked Library (DLL) and Visual Control Library (VCL) of real-time control and display functions. 3) Direct programming of internal DSP using provided source code examples and documentation. The DSP will support real-time sample-by-sample or block-by-block processing in order to implement a wide range of signal processing functions including filtering, adaptive noise cancellation, speech enhancement, dynamic gain adjustment, and frequency and amplitude compression among others. During Phase I the following work will be accomplished: 1) a DSP-based hardware system specifically designed for acoustical research with input amplifiers for microphones and output attenuators and speaker drivers will be developed. 2) Current USB 2.0 communications will be improved to 3.0. 3) Current DSP user development kit will be expanded to include additional speech processing routines with source code examples and documentation. 4) A VCL interface will be developed for TF32 in order to facilitate the incorporation of various speech processing routines into user developed applications. 5) Test data and validation procedures developed. 6) Signal and noise generation modules developed for system validation and testing. During Phase II: 1) A graphical interface will be developed in order to facilitate the development of DSP code. 2) A text book with examples and projects will be developed. 3) Improvements to the DSP-to-PC communications implemented. 4) A wireless and battery powered supply options developed.